(1) Field of the Invention
The present invention relates to an HBT and HFET integrated circuit (Bi-HFET) used as a high-frequency semiconductor device and to a manufacturing method thereof.
(2) Description of the Related Art
Hetero-junction bi-polar transistors (HBT), which utilize semiconductors with large bandgaps in emitters, are high-frequency analogue devices used in cellular phones and the like. In particular, InGaP/GaAs HBTs that use InGaP in emitters have low temperature dependence, and methods of using InGaP/GaAs HBTs for highly reliable devices are expected to continually multiply.
HBTs can be distinguished between an emitter-up type and a collector-up type. Generally, since the emitter-up type is superior to the collector-up type in processability, HBTs of the emitter-up type are presently mass produced. The HBTs of the collector-up type can decrease the base-collector capacity (Cbc) and is superior in this characteristic. However, since the emitter layer under the base electrode must be insulated and the manufacturing processes are complicated, the HBTs of the collector-up type have not been practically implemented.
Additionally, research and development have advanced for integrated circuits which integrate an HBT and an HFET that control a power amplifier (PA) including the HBT, using a switch device (SW) including the hetero-junction electric field effect transistor and the like. Thus, Bi-HFET process technology which forms an HBT and an HFET on the same substrate has attracted attention.
As the conventional Bi-HFET technology, there is a technology described for example in Japanese Unexamined Patent Application Publication No. 6-209077 in which an HBT and an HFET are formed on the same substrate. The prior art is described using the diagram below.
FIG. 1 is a cross section image which shows the structure of a conventional semiconductor device.
The semiconductor device has a region in which an HBT is formed (HBT region) and a region in which an HFET is formed (HFET region).
First, in the HBT region, an n-GaAs emitter cap layer 501, an n-AIGaAs emitter layer 502, a p-GaAs base layer 503, a non-doped GaAs collector layer 504a, an n-AlGaAs sub-collector layer 505a having a band gap larger than a band gap of the collector layer 504a, and an n-InGaAs collector cap layer 506 are sequentially laminated on a semi-insulating GaAs substrate 500.
On the other hand, in the HFET region, the emitter cap layer 501, the emitter layer 502, and the base layer 503 are sequentially formed on the semi-insulating GaAs substrate 500. Further, the following layers are sequentially laminated on the base layer 503, namely: a non-doped GaAs collector layer 504c which is positioned apart from the collector layer 504a, is made of the same material as the collector layer 504a, and on which a channel layer 504b is formed; an electron donor layer 505b made of the same material as the sub-collector layer 505a which is positioned apart from the sub-collector layer 505a; and a collector cap layer 506.
A method for manufacturing the semiconductor device which includes the above structure includes a step of etching the collector cap layer 506 into a predetermined shape, thus exposing a surface of an n-AIGaAs layer. Additionally, the method includes: a step of etching the n-AIGaAs layer and the non-doped GaAs layer into a predetermined shape, thus: forming the sub-collector 505a, the electron donor layer 505b that is positioned apart from the sub-collector 505a, the collector layer 504a, and the collector layer 504c that is positioned apart from the collector layer 504a; and exposing a surface of the base layer 503. Additionally, the method includes a step of etching the base layer 503 and the emitter layer 502 into a predetermined shape.
In the HBT region, a collector electrode 511, a base electrode 512, and an emitter electrode 513 are formed on the collector cap layer 506, the base layer 503, and the emitter cap layer 501 respectively. On the other hand, in the HFET region, a source electrode 514 and a drain electrode 516 are formed on the collector cap layer 506, and a gate electrode 515 is formed on the electron donor layer 505b. 